Huawei has released new data supporting its Tau (τ) Scaling approach, demonstrating that increased transistor density does not necessarily result in higher power consumption. According to research presented by Huawei semiconductor chief He Tingbo in a paper titled "Huawei's τ Chip Was Supposed to Melt?" posted on ChinaXiv, the Kirin 2026 chip achieves approximately 55% higher transistor density while reducing power consumption across multiple computing units at comparable performance levels. The measurements reveal significant power efficiency gains across key components.
The NPU achieved a 66% reduction in power consumption, the GPU demonstrated a 58% decrease, and the CPU performance core showed a 41% reduction, all while maintaining the same performance level. The NPU performance was particularly notable, maintaining 29 TOPS while operating at a 63% lower frequency and reducing voltage from 0.85V to 0.55V, resulting in a 73% decrease in power density. According to the paper, a substantial portion of chip energy consumption stems from data movement rather than computation itself.
Data movement accounts for more than 80% of the energy consumed by a SoC module. The Kirin design addresses this challenge through LogicFolding technology, which converts long horizontal interconnects into short vertical connections between stacked layers. This approach significantly reduces signal path lengths and decreases interconnect capacitance and energy consumption.
Typical core routing lengths can be reduced by 20%, with certain critical paths shortened by as much as 70%. The Kirin 2026 employs a 1.5-micrometer hybrid-bonding pitch with approximately 50 million vertical interconnects, of which 10-15% are utilized for signal transmission. Future iterations are already in development, with Kirin 2027 test silicon having reduced the hybrid-bonding pitch to 1 micrometer and more than 100 million vertical interconnects.
Huawei plans continued scaling over the next three years, targeting a pitch reduction to 720 nanometers with more than 200 million vertical interconnects. However, He cautioned that LogicFolding is not a complete solution and requires ongoing system-level engineering and iteration. He emphasized that Tau represents a time-scaling law rather than an energy-scaling law, meaning that if designers use all saved time to increase frequency, power consumption could actually increase.
The technology still faces significant engineering challenges including hybrid-bonding pitch precision, wafer warpage management, alignment accuracy, and EDA tool adaptation, with further development needed over the next three to five years. The Kirin 2026 processor is expected to power Huawei's Mate 90 flagship series and the second-generation tri-fold Mate XT 2 smartphone, both scheduled for unveiling in September 2026. The Mate 90 opened for pre-orders on August 31, with official unveiling beginning September 7.
Source: Global Times, Huawei research paper on ChinaXiv, STAR Market Daily, EE Times China, Commercial Times
Source: trendforce.com